Can ASML’s Hyper-NA EUV Enable Sub-1nm Manufacturing?

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Patent Intelligence Report  ·  Lithography Technology Series

How Hyper-NA EUV could redefine
sub-1nm semiconductor manufacturing

A data-backed assessment of patent landscapes, leading stakeholders, and the significance of next-generation lithography — connecting how the technology works to who is innovating, who is filing, and what it means for IP and technology strategy.

>0.55 NABeyond High-NA EUV
Sub-1nmTarget process node
ASMLDevelopment lead
imecResearch collaboration
View table of contents

Report details

Hyper-NA EUV — Technology & Patent Intelligence Report

Publisher Scintillation Research
Technology focus Hyper-NA EUV Lithography
Target node Sub-1nm manufacturing
Key stakeholders ASML, imec, TSMC, Samsung, Intel
IP coverage Patent landscape + whitespace
Patent sections 8-part landscape analysis
Audience IP, R&D, Strategy, Investment
>0.55 Numerical aperture
Sub-1nm Target manufacturing
EUV+ Beyond High-NA
IP 8-part patent analysis
360° Ecosystem coverage
Introduction

The lithography frontier beyond High-NA EUV

The global semiconductor industry is advancing rapidly as demand grows for more powerful processors, AI accelerators, advanced memory devices, and high-performance computing systems.

As chipmakers continue pursuing smaller process nodes, conventional EUV lithography faces increasing challenges related to pattern resolution, process complexity, overlay accuracy, and manufacturing efficiency. High-NA EUV (0.55 NA) has been introduced to extend scaling, while future technology roadmaps are evaluating even higher numerical apertures to support next-generation semiconductor manufacturing.

To address these challenges, the lithography ecosystem is exploring Hyper-NA EUV — a potential future evolution of EUV technology designed to deliver improved imaging resolution and patterning capability beyond current High-NA systems. Hyper-NA concepts focus on advanced optical architectures, anamorphic imaging systems, next-generation photoresists, mask technologies, and precision metrology.

Development efforts are led by ASML in collaboration with semiconductor manufacturers and research organizations, including imec and major chipmakers, as the industry investigates pathways for sustaining semiconductor scaling beyond the limits of existing lithography platforms. This report connects that technical picture to the intellectual-property activity surrounding the technology — enabling readers to move from "how the technology works" to "who is innovating, who is filing, and what it means for IP and technology strategy."

Report structure

Table of contents

Ten chapters connecting Hyper-NA EUV's technical foundations to patent landscape intelligence and commercialization strategy. Click any chapter to expand its sections.

— Condensed findings on Hyper-NA EUV technology, key patent holders, filing trends, and strategic implications for the sub-1nm lithography ecosystem
2.1 Who Will Benefit from This Report — lithography engineers, IP counsel, semiconductor strategists, equipment investors, and research professionals
3.1 Challenges in Conventional EUV and Lithography Technologies — resolution limits, multi-patterning complexity, overlay accuracy, stochastic defects, and throughput constraints
4.1 Key Features — advanced optical architectures, anamorphic imaging systems, next-generation photoresists, mask and pellicle innovations, precision metrology
4.2 Problems Hyper-NA EUV Aims to Solve — pattern resolution ceiling, multi-patterning dependence, overlay degradation, stochastic noise, and process integration complexity
4.3 Potential Applications — logic semiconductors, advanced memory, AI hardware, HPC processors, and future sub-1nm manufacturing nodes
— Technology development roadmap beyond High-NA EUV, ecosystem readiness, ASML and foundry timelines, cost and adoption outlook
6.1 Methodology & Scope — patent database coverage, search strategy, classification framework, and analytical approach
6.2 Top Assignees — leading patent filers including ASML, Carl Zeiss, imec, TSMC, Samsung, Intel, and emerging players; notable assignee profiles
6.3 Filing Activity Over Time — trend analysis identifying R&D acceleration points and technology maturity signals in Hyper-NA IP
6.4 Jurisdiction Coverage — USPTO, EPO, KIPO, TIPO, CNIPA, WIPO distributions across lithography-intensive patent offices
6.5 Technology Segmentation — how patents map to optics, illumination, photoresists, masks, metrology, pellicles, and system integration
6.6 Foundational Anchor Patents — core patents defining the Hyper-NA EUV IP landscape and their strategic significance
6.7 Representative Publications Across the Field — notable academic and industry publications shaping Hyper-NA EUV research direction
6.8 Whitespace & Strategic Opportunities — unprotected technology domains and emerging filing opportunities across the Hyper-NA ecosystem
— Stakeholder-specific takeaways for lithography engineers, IP counsel, foundry strategists, equipment investors, and semiconductor research professionals
— Synthesis of Hyper-NA EUV's technical trajectory, IP landscape dynamics, and strategic implications for sub-1nm semiconductor manufacturing
— Publisher profile, methodology, and service overview — patent analytics, technology scouting, competitive intelligence, and strategic research
— Full legal disclaimer covering information accuracy, IP ownership, and terms of use for this intelligence report
Inside Hyper-NA EUV Technology

Key features & technical innovations

Hyper-NA EUV combines advanced optical architectures with next-generation photoresist and metrology systems to push patterning resolution beyond the physical limits of current High-NA EUV platforms.

Hyper-NA optical architecture
Numerical aperture beyond 0.55 NA — next step beyond High-NA EUV — enabling finer pattern resolution for sub-1nm semiconductor manufacturing.
Anamorphic imaging systems
Asymmetric optical magnification designed to manage the extreme field-size constraints introduced by very high numerical aperture EUV systems.
Next-generation photoresists
Metal-oxide and novel chemically amplified resists engineered for higher photon sensitivity, reduced stochastic noise, and improved edge placement accuracy at Hyper-NA exposure conditions.
Mask & pellicle innovations
Advanced EUV mask substrates, absorber materials, and high-transmission pellicles designed to withstand the thermal and photon flux demands of Hyper-NA systems.
Precision metrology
Overlay measurement and inspection systems capable of sub-angstrom accuracy required for Hyper-NA pattern registration across multi-layer semiconductor structures.
Reduced multi-patterning dependence
Higher NA enables single-exposure patterning of features that currently require costly and complex multi-patterning sequences, improving process yield and throughput.
ASML & imec co-development
Hyper-NA development led by ASML in collaboration with imec and major foundries — ensuring early ecosystem alignment across optics, resists, masks, and process integration.
Sub-1nm node enablement
Hyper-NA is positioned as the lithography platform capable of sustaining Moore's Law into the sub-1nm era, where current EUV and High-NA systems reach fundamental resolution limits.
Challenges addressed

Limitations of conventional EUV & High-NA EUV

Hyper-NA EUV directly targets five compounding constraints that will prevent current EUV platforms from sustaining semiconductor scaling into the sub-1nm era.

01
Pattern resolution ceiling
High-NA EUV at 0.55 NA approaches its physical resolution limit for the feature sizes required by sub-1nm nodes. Hyper-NA pushes the numerical aperture further to restore resolution headroom
Resolution
02
Multi-patterning process complexity
Current EUV requires multiple costly patterning steps to achieve sub-10nm features. Hyper-NA aims to enable single-pass patterning of critical layers, reducing process steps and improving yield
Process
03
Overlay accuracy degradation
As feature sizes shrink, overlay errors between successive patterning layers become increasingly disruptive. Hyper-NA systems require and enable sub-angstrom overlay precision to maintain device yield
Accuracy
04
Stochastic defects & photon noise
At extreme feature sizes, statistical variation in photon absorption causes edge placement errors and line roughness. Next-generation photoresists and illumination systems in Hyper-NA address this fundamental noise floor
Materials
05
Manufacturing efficiency & throughput
Multi-patterning and complex process flows reduce wafer throughput and increase cost per die. Hyper-NA's single-exposure capability for critical layers restores manufacturing efficiency at advanced nodes
Throughput
Hyper NA EUV report cover

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