Panel-Level Packaging for AI Chips

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Patent Intelligence Report  ·  Advanced Packaging Series

Panel-Level Packaging (PLP) for AI Chips

A data-grounded look at who is filing, where innovation is concentrated, and why PLP is becoming strategically critical for next-generation AI chip manufacturing and heterogeneous computing platforms.

A comprehensive technology and patent intelligence analysis of PLP for AI chips — examining fan-out panel-level packaging (FOPLP), chiplet integration, heterogeneous packaging, high-density redistribution layers (RDLs), high-bandwidth memory (HBM) integration, thermal management, power delivery architectures, and advanced substrate technologies enabling next-generation AI and high-performance computing systems.

FOPLPFan-out panel-level packaging
ChipletHeterogeneous integration
HBMHigh-bandwidth memory
10-partPatent landscape analysis
View table of contents

Report details

Panel-Level Packaging (PLP) for AI Chips — Technology & Patent Intelligence Report

Publisher Scintillation Research
Technology Panel-Level Packaging (PLP)
Focus area AI Accelerators & HPC
Key segments FOPLP, Chiplet, HBM, RDL, Thermal
IP coverage 10-part patent landscape
Applications AI, Data Centers, HPC, Edge, Automotive
Audience IP, R&D, Strategy, Investment
PLP Panel-level packaging
8+ Technology segments
FOPLP Fan-out panel architecture
IP 10-part patent analysis
360° Ecosystem coverage
Introduction

When wafer-based advanced packaging can no longer meet the cost and throughput demands of AI chip manufacturing

The global semiconductor industry is undergoing a significant transformation as artificial intelligence, high-performance computing, data centers, and edge devices drive demand for greater computing power, memory bandwidth, and energy efficiency. As conventional transistor scaling becomes increasingly challenging, advanced packaging technologies are emerging as key enablers of next-generation semiconductor performance.

AI training and inference workloads, cloud-scale computing platforms, and heterogeneous chip integration all require packaging solutions that deliver higher throughput, lower cost per unit, and improved manufacturing efficiency at scale. Conventional wafer-based advanced packaging — including fan-out wafer-level packaging (FOWLP) and 2.5D/3D wafer-level approaches — continues to face limitations in panel utilization rates, throughput per process step, material costs, and scalability as AI chip designs grow in area and complexity.

To address these constraints, the industry is developing panel-level packaging technologies that replace circular wafers with large rectangular panels — enabling higher production throughput, better material utilization, and meaningfully reduced packaging costs. PLP enables the integration of multiple components, including processors, memory, chiplets, and accelerators, into a single package — helping to meet the performance and connectivity requirements of modern AI applications.

As investments in advanced packaging continue to grow, PLP is expected to play an increasingly important role in the commercialization of future AI chips and heterogeneous computing platforms beyond 2027. The patent landscape reflects broad engagement across OSAT leaders, IDMs, foundries, substrate specialists, and equipment vendors — each staking out IP positions ahead of expected PLP volume production ramp.

Report structure

Table of contents

Ten chapters connecting PLP's technical foundations to patent landscape intelligence and commercialization strategy. Click any chapter to expand.

— Condensed findings on PLP technology, top patent assignees, filing trends, competitive dynamics, and strategic implications for AI chip manufacturing, advanced packaging, and heterogeneous computing IP
2.1 Who Will Benefit from This Report — packaging engineers, AI hardware teams, IP counsel, semiconductor strategists, OSAT and foundry business development professionals, and technology investors tracking advanced packaging
3.1 Challenges in Conventional Packaging Technologies for AI Chips — wafer utilization inefficiency, throughput constraints, cost scaling limits, heterogeneous integration complexity, and HBM co-packaging demands at AI chip scale
— Structural components — large rectangular panel format, embedded die, redistribution layers, chip-last and chip-first architectures, molding compounds, and panel-scale lithography approaches
4.1 Key Features — panel format advantages, higher throughput per process step, improved material utilization, chiplet co-integration, fine-pitch RDL routing, and scalability for large AI chip packages
4.2 Problems PLP Aims to Solve — wafer-edge utilization waste, throughput bottlenecks, cost of wafer-based fan-out, HBM integration complexity, and density limitations of conventional substrate-based packaging
4.3 Potential Applications — AI accelerators, data center compute, cloud HPC, edge AI, automotive electronics, telecommunications, and heterogeneous chiplet platforms beyond 2027
— PLP deployment roadmap, OSAT and foundry capacity investment timelines, panel size standardization challenges, equipment ecosystem maturity, and near-term commercialization opportunities for AI chip packaging beyond 2027
6.1 Methodology & Scope — patent database coverage, search strategy, classification framework, and analytical approach for PLP, FOPLP, and heterogeneous packaging for AI accelerator IP
6.2 Scope Corrections — refinements addressing classification overlap between PLP, FOWLP, 2.5D/3D packaging, and advanced substrate domains
6.3 Revised Assignee Picture — leading filers across OSAT, IDM, foundry, substrate, and equipment segments with notable assignee profiles
6.4 Filing Activity Over Time — trend analysis identifying R&D acceleration and IP maturity signals across PLP technology domains
6.5 Jurisdiction Coverage — USPTO, CNIPA, KIPO, JPO, EPO, WIPO, and TIPO distributions across the PLP patent landscape
6.6 Technology Segmentation — patents mapped to FOPLP, chiplet integration, heterogeneous packaging, RDL, HBM integration, thermal management, power delivery, and advanced substrates
6.7 Foundational Anchor Patents — core IP defining the PLP landscape and their strategic competitive significance for AI chip packaging
6.8 Representative Publications Across the Field — key academic and industry publications shaping PLP research direction and deployment
6.9 Whitespace & Strategic Opportunities — underprotected technology domains and emerging filing opportunities across the PLP IP ecosystem
— Stakeholder-specific takeaways for packaging engineers, AI chip designers, IP counsel, OSAT and foundry strategists, equipment vendors, substrate specialists, and technology investors
— Synthesis of PLP's technical trajectory, IP landscape dynamics, and strategic implications for next-generation AI chip manufacturing, heterogeneous packaging, and advanced semiconductor commercialization
— Publisher profile, research methodology, and service overview — patent analytics, technology scouting, competitive intelligence, and strategic research across semiconductor and advanced packaging domains
— Full legal disclaimer covering information accuracy, IP ownership, and terms of use for this intelligence report
Inside Panel-Level Packaging

Structural components & key features

PLP replaces the circular wafer with large rectangular panels — the same form factor used in flat-panel display manufacturing — enabling significantly higher throughput, better edge utilization, and lower cost per packaged die for AI chip production at scale.

Fan-out panel-level packaging (FOPLP)
Core PLP architecture using large rectangular panels with embedded die and fan-out redistribution layers — enabling significantly higher throughput per process step than circular wafer-based fan-out approaches.
Chiplet integration
Die-to-die interconnect schemes enabling disaggregated chiplet architectures on PLP substrates — including hybrid bonding and advanced bump technologies for connecting logic, memory, and I/O chiplets from different process nodes.
Heterogeneous packaging
Co-packaging of dissimilar process nodes and materials — integrating logic, memory, photonics, and analog dies from different foundries and nodes into a single PLP form factor package for AI accelerator workloads.
High-density redistribution layers (RDL)
Fine-pitch multi-layer RDL innovations at panel scale enabling sub-2µm line/space routing — critical for the high-bandwidth die-to-die interconnect density required by AI accelerator and HBM integration in PLP packages.
HBM integration
High-bandwidth memory co-packaging on PLP substrates — enabling the multi-terabyte-per-second memory bandwidth required by AI training and inference accelerators, without the cost and throughput penalties of conventional 2.5D interposer approaches.
Thermal management
Heat dissipation architectures managing the combined thermal output of co-located AI compute dies, HBM stacks, and interconnect structures — including embedded cooling channels, thermal interface materials, and panel-scale heat spreaders.
Power delivery architectures
Integrated voltage regulation, power integrity, and PDN innovations at panel scale — enabling the current delivery density and voltage droop management required by high-TDP AI accelerator dies in PLP packages.
Advanced substrate technologies
Glass core, embedded trace, and ultra-low-loss substrate material innovations enabling PLP's roadmap beyond current organic substrate limitations — including warpage control, dimensional stability, and fine-pitch via technologies at panel scale.
Challenges addressed

Why conventional wafer-based packaging cannot scale to AI chip manufacturing demands

PLP directly targets five structural constraints that prevent conventional wafer-based advanced packaging from meeting the cost, throughput, and integration requirements of next-generation AI chip manufacturing at scale.

01
Wafer edge utilization waste
Circular wafers inherently waste the area near the wafer edge — typically 10–20% of usable area — as dies that fall across the edge cannot be packaged. PLP's rectangular panel format eliminates edge waste, improving material utilization and reducing effective cost per packaged die at AI chip dimensions
Utilization
02
Throughput constraints at scale
Wafer-based packaging processes each 300mm wafer as a discrete unit, limiting the number of dies processed per equipment cycle. Large-format panels process significantly more dies per pass through lithography, molding, and metallization equipment — directly improving throughput, reducing cycle time, and lowering cost per unit at AI packaging volumes
Throughput
03
Cost scaling limits for AI chip dimensions
As AI accelerator die sizes grow — with leading GPU and AI ASIC packages exceeding 800mm² — wafer-based fan-out packaging faces exponentially rising costs driven by large-area photolithography, warpage control challenges, and low yields on oversized packages. PLP's panel-native process is architected for large-format packages from the ground up
Cost
04
Heterogeneous integration complexity
Modern AI accelerators require the co-packaging of dies from multiple process nodes and suppliers — logic, HBM, I/O, and analog — with sub-micron placement accuracy. PLP's panel-scale embedded die and chiplet integration approaches address this complexity at higher throughput than wafer-level multi-chip module alternatives
Integration
05
HBM co-packaging at AI chip scale
High-bandwidth memory co-packaging for AI accelerators demands large substrate areas to place multiple HBM stacks adjacent to GPU or AI ASIC dies — areas that strain the cost and warpage management capabilities of conventional wafer-based packaging. PLP's panel format and substrate technologies are designed to accommodate the footprint and flatness requirements of multi-HBM AI accelerator packages
Memory
Panel level packaging report cover

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