Chip-level Reverse Engineering

Chip-level reverse engineering is the analysis of a semiconductor device down to the structures on the die. The package is removed, layers are exposed one at a time, and each is imaged and characterised until the circuit can be reconstructed. The output describes the functional architecture of the integrated circuit: which blocks are present, how they connect, and what materials sit in each layer. Licensing teams value it because it shows how a product works rather than how it is described.

A set of complementary physical techniques carries the work. Scanning electron microscopy, SEM, images the exposed structures. Transmission electron microscopy, TEM, resolves thin cross sections where individual layers matter. Electron energy loss spectroscopy, EELS, and energy dispersive X-ray spectroscopy, EDX, identify the elements present in those layers. Secondary ion mass spectrometry, SIMS, measures composition through the depth of the sample. Used together they give both the geometry of the device and the materials it is built from.

A product teardown works at the level of the board and its components: which parts a product contains, how they connect, and who supplied each one. Chip-level reverse engineering goes inside one of those components. It answers what a teardown cannot, such as how a function is implemented in silicon, which materials were used, and whether a particular structure is present at all. The two fit together, since a teardown is what identifies the chip worth analysing.

The analysis reveals the functional architecture of the integrated circuit, and that is the level at which many patent claims are written. It becomes useful the moment a discussion turns on whether a device really implements a given structure or signal path, because the answer then rests on physical evidence rather than a datasheet or a marketing claim. The images and material analysis stay on record, so one round of work can support several conversations about the same product.